I. Introduction
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present input but also on the history of the input. This is in contrast to combinational logic, whose output is a function of, and only of, the present input. In other words, sequential logic has state (memory) while combinational logic does not.
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present input but also on the history of the input. This is in contrast to combinational logic, whose output is a function of, and only of, the present input. In other words, sequential logic has state (memory) while combinational logic does not.
Sequential logic is therefore used to construct some types of computer memory, other types of delay and storage elements, and finite state machines. Most practical computer circuits are a mixture of combinational and sequential logic.
Executed sequentially.
Also called behavioral code.
Part of code that is executed sequentially:
Processes
Functions
Procedures
Variables are also restricted to be used in sequential code only.
II. Objective
To be able to create a sequential logic with sequential code
III.Conceptual Framework
IV. Data and Result
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity segmt_count is
port( set,clk,rst,pause : in std_logic;
I : in std_logic_vector (0 to 3);
segs :buffer std_logic_vector(6 downto 0);
rco : out std_logic);
end segmt_count;
architecture behav of segmt_count is
begin
process(clk, rst, set, pause)
begin
if(rst='0') then segs <= "0000001";
elsif(set ='0') then
case I is
when "0000" => segs <= "0000001";
when "0001" => segs <= "1001111";
when "0010" => segs <= "0010010";
when "0011" => segs <= "0000110";
when "0100" => segs <= "1001100";
when "0101" => segs <= "0100100";
when "0110" => segs <= "0100000";
when "0111" => segs <= "0001111";
when "1000" => segs <= "0000000";
when "1001" => segs <= "0000100";
when others => segs <= "1111111";
end case;
elsif (clk'event and clk ='1') then
if (pause = '0' and (rst='0' or clk='0' or set='0')) then segs <= segs;
elsif(pause = '1') then
case segs is
when "0000001" => segs <= "1001111";
when "1001111" => segs <= "0010010";
when "0010010" => segs <= "0000110";
when "0000110" => segs <= "1001100";
when "1001100" => segs <= "0100100";
when "0100100" => segs <= "0100000";
when "0100000" => segs <= "0001111";
when "0001111" => segs <= "0000000";
when "0000000" => segs <= "0001100";
when others => segs <= "0000001";
end case;
end if;
end if;
end process;
rco <= '1'when (segs = "0000001")else '0';
end behav;
V. Analysis and Discussion
In this experiment, we had four main problems: count, pause, reset and set. The group really got problems with this experiment. Unlike previous experiments, we spent three weeks to find out the errors. Also we got problems with the code and pin assignment. Finally, we were able to finish this experiment.
VI.Conclusion
By using sequential code we were able to create a sequential logic with the Mod -9 counter.By this experiment the group improved the debugging skills and increase the knowledge in programming especially the conditional and case statements.
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