I. Introduction
VHSIC (Very High Speed Integrated Circuits) Hardware Description Language
Used to describe the behavior of an electronic circuit or system
Two applications of VHDL
Programmable Logic Devices
Application Specific Integrated Circuits.
Click here for more information.
II. Objective
To be able to implement logic circuit design in VHDL code.
III. Conceptual framework
1. Concurrent Execution
VHDL statements are inherently concurrent (parallel)
For this reason, VHDL is usually referred to as a code rather than a program.
Only statements inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially.
2. Advantages of Using VHDL
Allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).
Allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time).
Supports in-system programmability.
◦ Program and reprogram devices after they are soldered onto the printed circuit board (PCB), minimizing the possibility of lead damage or electrostatic discharge (ESD) exposure.
Upgrade systems in the field after they have been shipped.
III. Data and Result
1. Experiment 2A
Data
library IEEE;
use IEEE.std_logic_1164.all;
entity DEC is
port( A, B, C, D : in bit;
E, F, G, H, I, J, K : out bit );
end DEC;
architecture DEC1 of DEC is
begin
E <= NOT((NOT A AND B AND D) OR
(A AND NOT B AND NOT C) OR
(NOT B AND NOT D) OR
(NOT A AND C) OR
(B AND C));
F <= NOT((NOT A AND NOT C AND NOT D) OR
(NOT A AND C AND D) OR
(A AND NOT C AND D) OR
(NOT B AND NOT C) OR
(NOT B AND NOT D));
G <= NOT((NOT B AND NOT C) OR
(NOT B AND D) OR
(NOT C AND D) OR
(NOT A AND B) OR
(A AND NOT B));
H <= NOT((NOT B AND NOT C AND NOT D) OR
(NOT B AND C AND D) OR
(NOT A AND C AND NOT D) OR
(B AND NOT C AND D) OR
(A AND B AND NOT D) OR
(A AND NOT C));
I <= NOT((NOT B AND NOT D) OR
(C AND NOT D) OR
(A AND B) OR
(A AND C));
J <= NOT((NOT B AND NOT C AND NOT D) OR
(NOT A AND B AND NOT C) OR
(B AND C AND NOT D) OR
(A AND C) OR
(A AND NOT B));
K <= NOT((NOT B AND C) OR
(B AND NOT C) OR
(B AND NOT D) OR A);
end DEC1;
Result:
2. Experiment 2B
Data
library IEEE;
use IEEE.std_logic_1164.all;
entity MUX is
port( s0, s1, s2, a, b, c, d, e, f, g, h : in bit;
y : out bit );
end MUX;
architecture MUX1 of MUX is
begin
y <= (a AND NOT s0 AND NOT s1 AND NOT s2) OR
(b AND NOT s0 AND NOT s1 AND s2) OR
(c AND NOT s0 AND s1 AND NOT s2) OR
(d AND NOT s0 AND s1 AND s2) OR
(e AND s0 AND NOT s1 AND NOT s2) OR
(f AND s0 AND NOT s1 AND s2) OR
(g AND s0 AND s1 AND NOT s2) OR
(h AND s0 AND s1 AND s2);
end MUX1;
Result
V. Analysis
In this experiment 2, programming defines the whole circuit design. First we have made some errors in the program because we are not familiar with the other functions of Quartus II. Apparently we have the notes in the powerpoint presentation and use the functions that is specified in the slides. So this experiment was easy because we need to know the different functions of the Quartus II and we have to analyze and understand the problem very well.
VI. Conclusion
In this experiment, our group were able to create a logic circuit using VHDL. We were able to use Quartus II version 11 software to create the VHDL. The experiment was easy for us and it focused on the programming. But we cannot avoid those errors except for the warning part. In this software it can directly show the errors in our program.
In this experiment, our group were able to create a logic circuit using VHDL. We were able to use Quartus II version 11 software to create the VHDL. The experiment was easy for us and it focused on the programming. But we cannot avoid those errors except for the warning part. In this software it can directly show the errors in our program.
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