Lab 3: Concurrent Code

 I. Introduction

Concurrent codes are a form of superimposed codes that can be decoded efficiently. It turns out that this property enables the development of a new form of spread spectrum radio communication that offers new ways to address several problems. The key ones that have been identified to date include:

• Unkeyed jam resistance in adversarial environments.

• Jam resistance in public-access networks.

• RFID self-jamming.

• MAC (Media Access Control) protocol simplification in wireless networks.

• Clock recovery and synchronization.

II. Objective

To be able to implement combinational logic circuits with concurrent code and interfaces their symbols with each other.

III. Conceptual Framework

IV. Data and Result

3.1 3.1 Create a multiplexer for two 4 bits numbers

library IEEE;
use IEEE.std_logic_1164.all;

entity twone is
port (A, B : IN STD_LOGIC_VECTOR(3 downto 0);
S : IN BIT;
X : OUT STD_LOGIC_VECTOR(3 downto 0));
end twone;

architecture fourbit of twone is
begin

process (S)
begin
if (S = '0') then
X<=A;
else
X<=B;
end if;
end process;
end fourbit;

3.2 Design a Comparator for two 4 bits numbers using VHDL. If A>B, the output is 1.


LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity twofour is
port (x, y : IN BIT_VECTOR (3 downto 0);
z : OUT BIT);
end twofour;

architecture behavior of twofour is
begin
z<= '1' when (x>y) else '0';
end behavior;

3.3 Design comparator for two 4 bits numbers in 7-segment. The 7-segment will display the greater number

IV. Analysis and Discussion

In experiment 3.1, we design a multiplexer for a 2 - 4 bit numbers. This part of the experiment tells us that when  A>B then the output is "1:". But if we switch it, B>A then output is "1". Or simply vice versa.

In experiment 3.2, we design a comparator for a 2 - 4 bit numbers. This part of the experiment tell us that if A>B then output is "1" but if B>A then the output is "0".

In experiment 3.3, we design a comparator for a 2 - 4 bit numbers displaying in 7-segment. In this experiment, its a combination of experiment 2.1, 3.1, and 3.2. The output of this is just like in 3.1 but displaying in the 7-segment.

V.Conclusion

            In this experiment, the group was able to implement combinational logic circuit with concurrent codes. At first, we have some difficulties in understanding the flow of the whole circuit and also for the codes. But then, we took the solution of understanding the flow of the inputs and outputs in the comparator. Finally, the resultant output of the comparator, we took it as an input for the multiplexer circuit design.